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1 ? fn7335.5 el7583 3-channel dc/dc converter the el7583 is a 3-channel dc/dc converter ic which is designed primarily for use in tft-lcd applications. it features a pwm boost converter with 2.7v to 14v input capability and 5v to 17v output, which powers the column drivers and provides up to 470ma @ 12v, 370ma @ 15v from 5v supply. a pair of charge pump control circuits provide regulated outputs of v on and v off supplies at 8v to 40v and -5v to -40v, respectively, each at up to 60ma. the el7583 features adjustable switching frequency, adjustable soft start, and a separate output v on enable control to allow selection of supply start-up sequence. an over-temperature featur e is provided to allow the ic to be automatically protec ted from excessive power dissipation. the el7583 is available in a standard 20 ld tssop package and the pb-free 20 ld htssop package. both are specified for operation over the full -40c to +85c temperature range. features ? tft-lcd display supply - boost regulator -v on charge pump -v off charge pump ? 2.7v to 14v v in supply ?5v < v boost < 17v ?5v < v on < 40v ? -40v < v off < 0v ?v boost = 12v @ 470ma ?v boost = 15v @ 370ma ? high frequency, small inductor dc/dc boost circuit ? over 90% efficient dc/dc boo st converter capability ? adjustable frequency ? adjustable soft-start ? adjustable outputs ? small parts count ? pb-free plus anneal available (rohs compliant) applications ? tft-lcd panels ?pdas pinout el7583 (20 ld tssop/htssop) top view ordering information part number part marking tape & reel package pkg. dwg. # el7583ir 7583ir - 20 ld tssop mdp0044 el7583ir-t7 7583ir 7? 20 ld tssop mdp0044 el7583ir-t13 7583ir 13? 20 ld tssop mdp0044 el7583irez (see note) 7583irez - 20 ld htssop (pb-free) mdp0048 el7583irez-t7 (see note) 7583irez 7? 20 ld htssop (pb-free) mdp0048 EL7583IREZ-T13 (see note) 7583irez 13? 20 ld htssop (pb-free) mdp0048 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. rosc enp enbn vref pgnd pgnd drvp vddp fbp vssp vssb ss fbb vddb lx lx lx drvn vddn fbn refer to pcb layout guideline 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 data sheet may 12, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003, 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7335.5 may 12, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute m aximum ratings (t a = 25c) v in input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14v v ddb , v ddp , v ddn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18v maximum continuous output current . . . . . . . . . . . . . . . . . . . . 0.5a storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c die junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v in = 3.3v, v boost = 12v, r osc = 100k ? , t a = 25c unless otherwise specified parameter description conditions min typ max unit dc/dc boost converter iq1_b quiescent current - shut-down enbn = enp = 0v 0.8 10 a iq2_b quiescent current - switching enbn = v ddb 4.8 8 ma v(fbb) feedback voltage 1.275 1.300 1.325 v v ref reference voltage 1.260 1.310 1.360 v v rosc oscillator set voltage 1.260 1.325 1.390 v i(fbb) feedback input bias current 0.1 a v ddb boost converter supply range 2.7 17 v d max maximum duty cycle 85 92 % i(lx) max peak internal fet current 1.75 a r ds-on switch on resistance at v boost = 10v, i(lx) total = 350ma 0.22 ? i leak-switch switch leakage current i(lx) total 1 a v boost output range v boost > v in + v diode 517v ? v boost / ? v in line regulation 2.7v < v in < 13.2v, v boost = 15v 0.1 % ? v boost / ? i o1 load regulation 50ma < i o1 < 250ma 0.5 % f osc-range frequency range r osc range = 240k ? to 60k ? 200 1000 khz f osc1 switching frequency r osc = 100k ? 620 680 750 khz positive regulated charge pump (v on ) most positive v on output depends on the magnitude of the v ddp input voltage (normally connected to v boost ) and the external component configuration (doubler or tripler) v ddp supply input for positive c harge pump usually connected to v boost output 5 17 v iq1(v ddp ) quiescent current - shut-down enp = 0v 11.5 20 a iq2(v ddp ) quiescent current - switching enbn = enp = v ddb 2.3 5 ma v(fbp) feedback reference voltage 1.245 1.310 1.375 v i(fbp) feedback input bias current 0.1 a i(drvp) rms drvp output current v ddp = 12v 60 ma v ddp = 6v 15 ma ilr_v on load regulation 5ma < i l < 15ma -0.5 0.03 0.5 %/ma f pump charge pump frequency frequency set by r osc - see boost section 0.5*f osc el7583
3 fn7335.5 may 12, 2006 negative regulated charge pump (v off ) most negative v off output depends on the magnitude of the v ddn input voltage (normally connected to v boost ) and the external component configuration (doubler or tripler) v ddn supply input for negative char ge pump usually connected to v boost output 5 17 v iq1(v ddn ) quiescent current - shut-down enbn = 0v 1.2 10 a iq2(v ddn ) quiescent current - switching enbn = v ddb 2.3 5 ma v(fbn) feedback reference voltage -80 0 +80 mv i(fbn) feedback input bias current magnitude of input bias 0.1 a i(drvn) rms drvn output current v ddn = 12v 60 ma v ddn = 6v 15 ma ilr_v off load regulation -15ma < i l < -5ma -0.5 0.03 0.5 %/ma f pump charge pump frequency frequency set by r osc - see boost section 0.5*f osc enable control logic v hi-enx enable input high threshold x = ?bn?, ?p? 1.6 v v lo-enx enable input low threshold x = ?bn?, ?p? 0.8 v il(en?x?) logic low bias current x = ?bn?, ?p? = 0v 0.1 a il(enbn) logic high bias current enbn = 5v 7.5 15 a il(enp) logic high bias current enp = 5v 3.3 7.5 a over-temperature protection t ot over-temperature threshold 130 c t hys over-temperature hysteresis 40 c electrical specifications v in = 3.3v, v boost = 12v, r osc = 100k ? , t a = 25c unless otherwise specified (continued) parameter description conditions min typ max unit el7583
4 fn7335.5 may 12, 2006 pin descriptions i = input, o = output, s = supply pin number pin name pin type pin function 1 vssb s ground for dc/dc boost and reference circuits; chip substrate 2 ss i soft-start input; the capacitor connected to this pin sets the current limited start time 3 fbb i voltage feedback input for boost ci rcuit; determines boost output voltage, v boost 4 vddb s positive supply input for dc/dc boost circuits 5 lx o boost regulator inductor drive c onnected to drain of internal nfet 6 lx o boost regulator inductor drive c onnected to drain of internal nfet 7 lx o boost regulator inductor drive c onnected to drain of internal nfet 8 drvn o driver output for the external gener ation of negative charge pump voltage, v off 9 vddn s positive supply for input for v off generator 10 fbn i voltage feedback input to determine negative charge pump output, v off 11 vssp s negative supply pin for both the positive and negative charge pumps 12 fbp i voltage feedback to determine positive charge pump output, v on 13 vddp s positive supply input for v on generator 14 drvp o voltage driver output for the exte rnal generation of positive charge pump, v on 15 pgnd o power ground, connected to source of internal nfet 16 pgnd o power ground, connected to source of internal nfet 17 vref i voltage reference for charge pump circuits; decouple to ground 18 enbn i enable pin for boost (v boost generation) and negative charge pump (v off generation); active high 19 enp i enable for drvp (v on generation); active high 20 rosc i connected to an external resistor to ground; sets the switching frequency of the dc/dc boost el7583
5 fn7335.5 may 12, 2006 typical performance curves figure 1. efficiency vs i out figure 2. efficiency vs i out figure 3. efficiency vs i out figure 4. efficiency vs i out figure 5. f s vs v ddb figure 6. v ref vs temperature 0 100 200 300 400 500 600 700 800 95 90 85 80 75 70 65 60 55 50 i out (ma) efficiency (%) v in =3.3v freq=1mhz 15v 12v 9v 5v 0 100 200 300 400 500 600 700 800 95 90 85 80 75 70 65 60 i out (ma) efficiency (%) v in =5v freq=1mhz 15v 12v 9v 0 100 200 300 400 500 600 700 800 95 90 85 80 75 70 65 60 i out (ma) efficiency (%) v in =3.3v freq=700khz 15v 12v 9v 5v 0 100 200 300 400 500 600 700 800 95 90 85 80 75 65 60 i out (ma) efficiency (%) v in =5v freq=700khz 15v 12v 9v 70 970 968 966 964 962 33.5 6 v ddb (v) frequency (khz) 4.5 965 963 5.5 969 45 967 r osc = 61.9k ? 1.27 1.26 1.25 -50 150 temperature (c) voltage (v) 50 1.265 0100 1.255 el7583
6 fn7335.5 may 12, 2006 figure 7. load regulation vs i out figure 8. load regulation vs i out figure 9. load regulation vs i out figure 10. load regulation vs i out figure 11. v on vs i on figure 12. v off vs i off typical performance curves (continued) i out (ma) f=675khz, v in =5.0v 1.5 1.0 0.0 -0.5 -1.0 -1.5 0 100 300 500 700 load regulation (%) 0.5 400 600 200 15v 9v 12v 18v f=675khz, v in =3.3v 1.5 1.0 0.0 -0.5 -1.0 -1.5 0 100 200 300 500 700 800 i out (ma) load regulation (%) 0.5 400 600 18v 12v 9v 5v 15v i out (ma) f=1mhz, v in =5.0v 1.5 1.0 0.0 -0.5 -1.0 -1.5 0 100 300 500 700 load regulation (%) 0.5 400 600 200 15v 9v 12v 18v f=1mhz, v in =3.3v 1.5 1.0 0.0 -0.5 -1.0 -1.5 0 100 200 300 500 700 800 i out (ma) load regulation (%) 0.5 15v 9v 12v 400 600 18v 5v 20 19 18 17 16 15 14 010 20304050607080 i load (ma) v on (v) v ddp = 15v v ddp = 12v i load (ma) v off (-v) 6.5 6 5.5 5 4.5 4 3.5 010 2030 40 50 607080 v ddn = 15v v ddn = 12v el7583
7 fn7335.5 may 12, 2006 figure 13. f s vs r osc figure 14. f s vs r osc figure 15. power-down figure 16. power-up figure 17. lx waveform - discontinuous mode figure 18. lx waveform - continuous mode typical performance curves (continued) f(mhz)=1/(0.0118 r osc +0.378) 1400 1000 800 400 0 0 50 100 200 450 r osc (k ? ) frequency (khz) 150 300 600 200 400 1200 250 350 switching period(s)=0.0118 r osc +0.378) 6 4 3 1 0 0 50 100 200 450 r osc (k ? ) switching period (s) 150 300 2 400 5 250 350 100k & 0.1f delay network on enp, c ss =0.1f v boost v on v off 5v/div 2v/div 10v/div 200ms/div 100k & 0.1f delay network on enp, c ss =0.1f v boost v on v off 5v/div 2v/div 10v/div 1ms/div 1ms/div v in =3.3v, v out =11.3v, i out =50ma v in =3.3v, v out =11.3v, i out =250ma el7583
8 fn7335.5 may 12, 2006 functional block diagram figure 19. package power dissipation vs ambient temperature figure 20. package power dissipation vs ambient temperature typical performance curves (continued) 3.5 3 2.5 1.5 1 0.5 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 2.857w j a = 3 5 c / w h t s s o p 2 0 125 85 2 jedec jesd51-7 high effective thermal conductivity test board htssop exposed diepad soldered to pcb per jesd51-5 1.111w j a = 9 0 c / w t s s o p 2 0 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 85 0.8 0.5 0.7 125 800mw j a = 1 2 5 c / w h t s s o p 2 0 jedec jesd51-3 low effective thermal conductivity test board 714mw j a = 1 4 0 c / w t s s o p 2 0 start-up oscillator - + i lout pwm logic r osc enbn fbb v ddb lx v ssb pgnd ss max_duty v ref v ramp r 2 r 1 v out 10h v in 0.22 ? 160m ? 7.2k 12a pwm comparator reference generator r 3 62k ? 0.1f 10f 10f 13k ? 110k ? 49 ? 0.1f el7583
9 fn7335.5 may 12, 2006 applications information the el7583 is high efficiency multiple output power solution designed specifically for thin-film transistor (tft) liquid crystal display (lcd) applications. the device contains one high current boost converter and two low power charge pumps (v on and v off ). the boost converter contains an integrated n-channel mosfet to minimize the number of external components. the converter output voltage can be set from 5v to 18v with external resistors. the v on and v off charge pumps are independently regulated to positive and negative voltages using external resistors. output voltages as high as 40v can be achieved with additional capacitors and diodes. boost converter the boost converter operates in constant frequency pulse- width-modulation (pwm) mode. quiescent current for the el7583 is only 5ma when enabled, and since only the low side mosfet is used, switch drive current is minimized. 90% efficiency is achieved in most common application operating conditions. a functional block diagram with typical circuit configuration is shown on previous page. regulation is performed by the pwm comparator which regulates the output voltage by comparing a divided output voltage with an internal reference voltage. the pwm comparator outputs its result to the pwm logic. the pwm logic switches the mosfet on and off through the gate drive circuit. its switching frequency is external adjustable with a resistor from timing control pin (r osc ) to ground. the boost converter has 200khz to 1.2mhz operating frequency range. start-up after v ddb reaches a threshold of about 2v, the power mosfet is controlled by the start-up oscillator, which generates fixed duty-ratio of 0.5 - 0.7 at a frequency of several hundred kilohertz. this will boost the output voltage, providing the initial output cu rrent load is not too great (<250ma). when v ddb reaches about 3.7v, the pwm comparator takes over the control. the duty ratio will be decided by the multiple-input direct summing comparator, max_duty signal (about 90% duty-ratio), and the current limit comparator, whichever is the smallest. the soft-start is provided by the current limit comparator. as the internal 12a current source charges the external soft- start capacitor, the peak mosf et current is limited by the voltage on the capacitor. this in turn controls the rising rate of output voltage. the regulator goes through the start-up sequence as well after the enbn signal is pulled to hi. steady-state operation when the output reaches the pres et voltage, the regulator operates at steady state. de pending on the input/output condition and component, the in ductor operates at either continuous-conduction mode or discontinuous-conduction mode. in the continuous-conduction mode, the inductor current is a triangular waveform and lx voltage a pulse waveform. in the discontinuous-conduction mode, the inductor current is completely ?dried-out? before the mosfet is turned on again. the input voltage source, the inductor, and the mosfet and output diode parasitic capacitors forms a resonant circuit. oscillation w ill occur in this period. this oscillation is normal and wil l not affect the regulation. at very low load, the mosfet will skip pulse sometimes. this is normal. current limit the mosfet current limit is nominal i lmt = 1.75. this restricts the maximum output current i omax based on the following formula: where: ? ? i l is the inductor peak-to-peak current ripple and is decided by: ? d is the mosfet turn-on radio and is decided by: ?f s is the switching frequency. i omax i lmt ? l 2 ------ - ? ?? ?? v in v o --------- = ? i l v in l --------- d f s ------ - = d v o - v in v o ----------------------- - = el7583
10 fn7335.5 may 12, 2006 the following table gives typical values: (margins are considered 10%, 3%, 20%, 10%, and 15% on v in , v o , l, f s , and i lmt , respectively) component considerations input capacitor it is recommended that c in is larger than 10f. theoretically, the input capacitor has ripple current of ? i l . due to high-frequency noise in the circuit, the input current ripple may exceed the theoretical value. larger capacitor will reduce the ripple further. boost inductor the inductor has peak and average current decided by: the inductor should be chosen to be able to handle this current. furthermore, due to the fixed internal compensation, it is recommen ded that maximu m inductance of 10h and 15h to be used in the 5v and 12v or higher output voltage, respectively. the output diode has average current of i o , and peak current the same as the inductor's peak current. schottky diode is recommended and it should be able to handle those currents. feedback resistor network an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 200k ? is recommended. the boost converter output voltage is determined by the following relationship: where v fbb is 1.300v. a 1nf compensation capacitor across the feedback resistor to ground is recommended to keep the converter in stable operation at low output current and high frequency conditions. schottky diode speed, forward voltage drop, and reverse current are the three most critical specificat ions for selecting the schottky diode. the entire output current flows through the diode, so the diode average current is th e same as the average load current and the peak current is the same as the inductor peak current. when selecting the diode, one must consider the forward voltage drop at the peak diode current. on the elantec demo board, mbrm120 is selected. its forward voltage drop is 450mv at 1a forward current. output capacitor the el7583 is specially compensated to be stable with capacitors which have a worst-case minimum value of 10f at the particular v out being set. output ripple voltage requirements also determine the minimum value and the type of capacitors. output ripple voltage consists of two components - the voltage drop caused by the switching current though the esr of the output capacitor and the charging and discharging of the output capacitor: for low esr ceramic capacitors, the output ripple is dominated by the charging/di scharging of the output capacitor. in addition to the voltage rating, the output capacitor should also be able to handle the rms current is given by: positive and negative charge pump (v on and v off ) the el7583 contains two independent charge pumps (see charge pump block and connection diagram.) the negative charge pump inverts the v ddn supply voltage and provides a regulated negative output vo ltage. the positive charge pump doubles the v ddp supply voltage and provides a regulated positive output voltage. the regulation of both the negative and positive charge pumps is generated by the internal comparator that se nses the output voltage and compares it with and internal reference. the switching frequency of the charge pump is set to ? the boost converter switching frequency. the pumps use pulse width modulation to adjust the pump period, depending on the load present. the pumps are short- circuit protected to 180ma at 12v supply and can provide 15ma to 60ma for 6v to 12v supply. table 1. maximum continuous output current v in (v) v o (v) l (h) f s (khz) i omax (ma) 3.3 9 10 1000 430 3.3 12 10 1000 320 3.3 15 10 1000 250 5 9 10 1000 650 5 12 10 1000 470 5 15 10 1000 370 12 18 10 1000 830 i lpk i lavg ? i l 2 -------- + = i lavg i o 1 - d ------------- = v boost r 1 r 2 + r 1 -------------------- - v fbb = v ripple i lpk esr v out - v in v out ------------------------------- - + i out c out fs ------------------------------ = i corms 1 ( - d ) d ? i l 2 i lavg 2 ------------------- - + ? ? ? ? 1 12 ------ ? ? ? ? i lavg = el7583
11 fn7335.5 may 12, 2006 single stage charge pump positive charge pump design considerations a single stage charge pump is shown above. the maximum v on output voltage is determined by the following equation: where: ?r onn and r onp resistance values depend on the v ddp voltage levels. for 12v supply, r on is typically 33 ? . for 6v supply, r on is typically 45 ? . if additional stage is required, the lx switching signal is recommended to drive the additional charge pump diodes. the drive impedance at the lx switching is typically 220m ? . the figure below illustrates an implementation for two-stage positive charge pump circuit. - + + - osc - + r 21 r 22 v ref 3.3f 0.1f 5v to 17v v ddn drvn v ssn v ddp drvp v ssp fbp fbn v fbp r 11 r 12 2.2f 0.1f 5v to 17v v off v on r on is 30 - 40 ? for v dd 6v to 12v r onp r onn r onp r onn c out2 c cpn c cpp c out1 v on max () 2v ddcpp - i out 2r onn ( r onp ) - 2 v diode - i out 1 0.5 f s c cpp ------------------------------------------- - + - i out 1 0.5 f s c out1 ----------------------------------------------- - el7583
12 fn7335.5 may 12, 2006 two-stage positive charge pump circuit the maximum v on output voltage for n+1 stage charge pump is: r 11 and r 12 set the v on output voltage: where v fbp is 1.310v. negative charge pump design considerations the criteria for the negative c harge pump is similar to the positive charge pump. for a single stage charge pump, the maximum v off output voltage is: similar to positive charge pump, if additional stage is required, the lx switching signal is recommended to drive the additional charge pump diodes. the figure on the next page shows a two stage negative charge pump circuit. - + + - v ssp drnp fbp 1.265v v ddp c cpp c out1 v boost (5v-17v) v lx c out1 r 12 r 11 c cpp v on r onp r onn v on max () 2v ddp - i out 2r onn ( r onp ) - 2 v diode - i out 1 0.5 f s c cpp -------------------------------------------- + - i out 1 0.5 f s c out1 ----------------------------------------------- - nv lx max () - n 2 v diode i out 1 0.5 f s c cpp -------------------------------------------- + ? ? i out 1 0.5 f s c out1 ----------------------------------------------- - ? ? ++ v on v fbp r 11 r 12 + r 11 -------------------------- - = v off max () i out 2r onn ( r onp ) 2v diode - i out 1 0.5 f s c cpn -------------------------------------------- ++ - i out 1 0.5 f s c out2 ----------------------------------------------- - - v ddn el7583
13 fn7335.5 may 12, 2006 two-stage negative charge pump circuit the maximum v off output voltage for n+1 stage charge pump is: r 21 and r 22 determine v off output voltage: where v ref is 1.310v. over-temperature protection an internal temperature sensor continuously monitors the die temperature. in the event that die temperature exceeds the thermal trip point, the device will shut down and disable itself. the upper and lower trip points are typically set to 130c and 90c respectively. pcb layout guidelines careful layout is critical in the successful operation of the application. the following layout guidelines are recommended to achieve optimum performance. ?v ref and v ddb bypass capacitors should be placed next to the pins. ? place the boost converter diode and inductor close to the lx pins. ? place the boost converter output capacitor close to the pgnd pins. ? locate feedback dividers close to their respected feedback pins to avoid switching noise coupling into the high impedance node. ? switching output pcb traces s hould not cross, or be laid out adjacent to, feedback trac es without using a grounded shielding trace or layer. this is to prevent undesirable switching interactions coupling into the feedback inputs. ? place the charge pump feedback resistor network after the diode and output capacitor node to avoid switching noise. ? all low-side feedback resistors should be connected directly to v ssb . v ssb should be connected to the power ground close at one point only. a demo board is available to illustrate the proper layout implementation. - + v ssn drvn fbn v ddn c cpn c out2 v lx c out2 r 21 r 22 c cpn v ref v off 5v-17v r onn r onp v off max () i out 2r onn ( r onp ) 2v diode - i out 1 0.5 f s c cpn -------------------------------------------- ++ - i out 1 0.5 f s c out2 ----------------------------------------------- - - v ddn - n v lx max () n2v diode i out 1 0.5 f s c cpn -------------------------------------------- + ? ? + i out 1 0.5 f s c out2 ----------------------------------------------- - ? ? + v off -v ref r 21 r 22 --------- - = el7583
14 fn7335.5 may 12, 2006 typical application circuit * mbrm120lt3 ** bat54s 0.1f 0.1f c 11 c 12 r 11 3.9k r 12 51k c 16 0.1f c 17 2.2f v on (18v@18ma) l1 10h d1* r 4 49.9 c 6 0.1f c 22 0.1f c 21 0.1f d 21 ** r 21 154k c 26 3.3f c 27 0.1f r 22 33.2k v off (-6v@ 15ma) r 3 61.9k r 5 497k r 6 0 c 8 0.1f c 50 open c 3 22f c 4 open c 5 10f c 9 1nf c 10 open d 11 ** r 1 13k r 2 110k v boost (12v@ 500ma) c 2 4.7f c 1 10f v in gnd c 7 0.1f 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 + + rosc enp enbn vref pgnd pgnd drvp v ddp fbp vssp v ssb ss fbb v ddb lx lx lx drvn v ddn fbn el7583
15 fn7335.5 may 12, 2006 el7583 tssop package outline drawing
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7335.5 may 12, 2006 el7583 htssop package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp

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